This article is inspired by a good friend that is in the teaching field, who said to me “my students have a great interest in learning the real-life applications of digital control systems”. And I think it is time to put all the pieces together and tell the life story of digital design in the “real world”.
It started off with the fundamental of Logic design, where the sea of logic gates are put together to create a digital circuit; example an ALU, FiFo, Decoders, Memory, CPU, etc. All this information is entered through either a schematic or RTL (Register Transfer Language) and later get produced as IC (Integrated Circuit) chip which is put together to create your laptop, smart phone and many more devices.
There are 3 elements to make this happen, the design, the CAD tools and the foundry. In general, it started with an idea or a market need and later get translated into a technical specification. From there, designers will start coding his/her RTL. The language commonly used could be SystemVerilog, Verilog or VHDL. Some design uses schematic, but for this article I will focus on RTL based design.
It started with a piece of RTL code, written via any text editor. My generation will be using EMACS or VI. Once the code is done, we will have to test it before going through the “physical” flow. In order to test the RTL, a testbench is built and the design is subjected to test and verification. The basic CAD tool used is a “simulator”, in which the test-bench sends test information into the design. These vectors are captured by the simulator and RTL designer is to review the simulation results to confirm the functional correctness of the design. The commonly simulation tools used are Modelsim, VCS, irun/xrun, etc. There also other testing tools to verify the design, so kind of formal verification tools; like Cadence’s Jasper, RealIntent’s RDC/CDC, Spyglass for LINT checks. All that to verify the piece of RTL is good and ready for “physical implementation”. RDC/CDC is one of the most important checks, the word “RDC/CDC” means “Reset Domain Crossing/Clock Domain Crossing”. This check is to catch illegal domain crossing signal/clock to prevent design failure is early phase. If your design is “low power”, a set of RTL related “UPF” files will be use in verification, Cadence Conformal Low Power checks will be perform against the RTL. The “UPF” files which is also know as IEEE1081 standard, describes the low power behavior of the circuit. The UPF file is also used during the synthesis and Placed-and-Route stage too.
Now the RTL is more or less “good-to-go”, let synthesize it and get the design out the door. Not so fast!! This is the part where the foundry comes into the play. Based on the needs and cost, a specific technology and semi-conductor foundry (TSMC/UMC/Global Foundry) is picked for the design. The foundry will provide the DRM (Design Rule Manual) and “Standard-cell” libraries, etc. Basically, the whole set of “do-and-don’ts” is captured in some form of design rules and libraries; just like your raw materials in building anything. Hand-in-hand, the CAD vendors will provides the tools to utilize the rules and libraries. Once they are setup and ready to use, the RTL designer will read in the design via the the synthesis tool to generate a “netlist”. The synthesis tools I have used are Synopsys DC and Cadence Genus, both the tools work in a similar way. It will translate the RTL code based on its design constraint + “DFT” requirement to generate a Verilog “netlist‘. DFT stands for “Design Form Test”, which in general also refer to it as SCAN. All design needs to be testable, so that is can be rejected during manufacture when a device fault is observed. To keep thing simple, the word SCAN imply that the design is being “scan” through to check if it is behaving correctly. Traditionally, it is done through a series of “scan chains” via a scan clock, scan mode, scan enable signals; not forgetting the most important signal in the design; reset. The Verilog “netlist” is a industry standard of connecting the sea of gates into a functional representation of the design, with respect to the foundry delivered gate set. That is also the reason why it is called “net-list”, where gates are connected through a set of nets. Assuming we did all the checks and verified the netlist is good.
The next phase is to bring the design “netlist” into physical implementation. This is also known as the “Place and Route” (PnR) phase. This is usually handled by a PnR engineer which their skill set is quite different. The PnR engineer does not do RTL and front-end design, their main focus is to do floor-plan and power-rail design with respect to the technology used. The PnR tools commonly used in the industry are Synopsys ICC and Cadence Innovus. The foundry TECH LEF file is used to guide the tools in routing the design. In general, digital/logic design is bounded by the idea of “timing closure” and the critical job of the PnR engineer is to meet both the physical requirement and “timing closure” boundary. First, the “die” size estimation to create a rough floorplan and shape of the “die”. Then power grid is plan and created across the floorplan and specifically the “HARD MACRO/ MEMORIES” are critically pre-placed before the PnR run. Based on the design constraint, the design will be placed, clock-tree synthesized, routed. Finally, the design is DRC and timing clean, and it is ready to do a “Timing Signoff” of the design.
The “Static Timing Analysis” (STA) engineer will perform a complete timing checks across all functional and scan mode. The CAD tools used are Synopsys Primetime and Cadence Tempus, it is a timing analysis tool to evaluate the setup/hold time of the design. With “PnR” done, the SPEF file is used in the analysis to ensure the accuracy of the parasitic extraction. This phase strongly relay to the timing constraint of the design, generally also know as SDC file. The accuracy of the SDC is very critical and it will impact runtime and the design closure. With the general assumption of all logic design requires a clock and all data/signals are bound by the given clocks, the setup and hold time are evaluated through out the whole design. By narrowing the correct data/signal paths between blocks and IPs, the design is slowly shaped into its respective final timing sign-off constraint. This process mainly checks for timing requirement. The same “post-PnR” netlist will also be feed to the verification team to perform gate-level simulation. By using the SDF file provided by the STA engineer, the timing driven simulation is to cover all corner test cases to ensure the device is functionally correct with the SDF timing annotated.
Assuming the designer found a “bug” and the whole thing will need to go through a ECO phase and finally the GDS is release to the foundry for manufacture. These whole process is done across multiple function of engineers, no one man can do all this and “tape-out” a chip. It is a world engineering collaboration to ensure the design is fully tested and manufactured correctly before putting it on the circuit board. I hope this short summary help to bring some understanding of the semi-conductor world.
(NOTE:) Some details of the whole design cycle is left out due to the complexity the process. This article is to give a high level view of the digital/logic design world.
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